Carbon Nanotube Field Effect Transistors (CNFETs) are attracting more and more attentions due to their power and performance benefits. However, existing Carbon NanoTube (CNTs) growing techniques may produce a mixture of metallic CNTs (m-CNTs) and semiconductor CNTs (s-CNTs). m-CNTs may lead to source-drain shorts in CNFETs, resulting in excessive leakage and highly degraded noise margins. Thus, there is a need for m-CNT removal after growth of CNTs.
Existing techniques for m-CNT removal include CNT sorting, selective chemical etching, Single-Device electrical Breakdown (SDB), VLSI-compatible Metallic-CNT Removal (VMR), and the like. However, some of the existing techniques do not sufficiently remove m-CNTs. Some may also introduce restrictions. For example, the CNT sorting technique may impose restrictions on radial CNT alignment, and the selective chemical etching technique may impose restrictions on narrow CNT diameter distributions. The SDB technique can achieve almost 100% m-CNT removal, but is not VLSI compatible. The VMR technique is VLSI-compatible, but may introduce significant area penalties up to 200% when applied to full-wafer-scale.
In view of the above, there is a need for a method for removing metallic nanotubes to efficiently remove the metallic nanotubes, so as to quickly remove the metallic nanotubes at full-wafer-scale without area penalties.